1. Field of the Invention
The invention relates to the field of semiconductor integrated circuits, and more specifically, to an apparatus for generating an asynchronous status flag which has a defined minimum pulse width.
2. Prior Art
Flags are provided in a number of integrated circuits. Flags signal the present condition of a circuit. For example, in a microprocessor flags are used to signal when errors occur, or when the microprocessor is busy. In FIFO (first in, first out) memory devices an "EMPTY flag" is used to signal when the device is empty or not empty. A "FULL flag" is used to signal when the device is full of data or not full of data.
In a FIFO, an empty flag (EF), for example, is derived from two asynchronous signals, a clock read signal (CKR) and the clock write signal (CKW). As shown in FIG. 1, assume that a FIFO presently contains one word, a read signal (CKR) would read out the only word contained in the FIFO and cause the FIFO to go empty. The rising edge of the read clock signal (CKR) causes the empty flag (EF) to go low to signal a true empty condition (EF is an active low signal). The empty flag (EF) signal remains low (true) until new data is written into the FIFO. When a write clock signal (CKW) is generated to write new data into memory, the EF signal goes high indicating that the FIFO is no longer empty.
The EF status flag is referred to as an "asynchronous flag" because it is derived from two independent signals. That is, CKR and CKW are asynchronous signals, they have no predetermined or fixed time relationship to one another. (The CKR signal is generated by a system component which reads data out of the FIFO at one rate, while the CKW signal is generated by a different component which writes data into the FIFO at a second independent rate.) The CKR signal causes the falling edge of the EF signal and the CKW signal causes the rising edge of the EF signal. The active pulse length of the EF signal is defined by the time lapse between the CKR signal and the CKW signal.
As shown in FIG. 2, as the time lapse between the CKR signal and the CKW signal is decreased so is the active pulse length of the EF signal. If the time delay between the CKR signal and the CKW signal is decreased even further, as shown in FIG. 3, the active pulse length of the EF signal can become "miniscule". Such a small pulse length can cause several problems for sequential logic circuits located downstream of the asynchronous status flag generator. (Downstream circuits are circuits which use the asynchronous signal, i.e. the consumer of the signal.) For example, in some cases the EF signal is used as data in downstream circuits. Such "miniscule" pulse lengths can violate data set-up and hold times. In other cases, the EF signal is used as a dock to drive downstream circuits. Here, the small signals can violate minimum clock pulse length requirements for the circuits. Such "miniscule" pulses can cause downstream sequential logic circuits to go into metastable conditions.
Metastable conditions are highly undesirable and can cause severe reliability problems in circuits. Presently, a substantial amount of additional circuitry and expense must be added to a circuit which receives asynchronous flags in order to protect against such small pulses. That is, additional circuitry and engineering must be provided to protect circuits imputing asynchronous flags from "miniscule" pulses which can cause the circuits to go into metastable conditions.
Thus, what is needed is an apparatus which generates an asynchronous status flag without generating "miniscule" pulses and their undesirable effects.